Tag Archives: QFN

Land Patterns – Equal and Not Equal

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I was recently asked a question about QFN package varieties. The questioner wanted to know if different package variants of 16 contact QFN packages, such as HUQFN, DHVQFN, SQFN and such, all shared the same footprint.

If they did, the CAD work would be much easier. There would be one land pattern to worry about and that would be that. Unfortunately, that is not that and in this case, that, in fact, that may never be that.

Many different varieties of QFN packages could use the same land pattern, but they don’t always do. Some will have the same pitch, but more distance between the outside contacts and the corner, thus a greater overall dimension. That can happen even with the same labeled variety of QFN package. Some will have different dimensions, differnt pitch, different pad sizes or different thermal pad sizes. Sorry. No easy answer here.

I popped on over to the NXP website, one of our Circuit Design ECOsystem partners, for some examples. NXP lists two 60 contact HUQFN part packages. One is 5 x 5 mm. The other is 6mm x 4mm. Same with the HVQFN. There is a 0.65 mm pitch, 4 x 4mm package and two 0.5 mm pitch, 3 x 3mm parts with a different overall package outline.

In general, generalzations aren’t going to work here. You’re going to have to go dig out that datasheet and quite possibly create a new land pattern.

Duane Benson
One pattern to rule them all and in the solder bind them

http://blog.screamingcircuits.com/

AT Tiny is Tiny

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ATTINY44A-MMH I just spotted a note on Twitter, from SiliconFarmer, referring to the ATtiny44A coming in a 0.45 mm pitch QFN as well as a 0.5mm pitch MLF package. (In practice, an MLF is the same as a QFN, by the way.) (Just in case you actually care, we’re on Twitter at “pcbassembly.”)

I’ve run across a number of 0.4 mm BGA packaged parts, but this is the first sub-0.5 mm QFN I’ve seen. Interesting that they have two different sizes of QFN package, one at 4 x 4 mm and the other at 3 x 3mm. If you’re that tight on space, that little 7 square mm of extra open area can make a difference.

Screaming Circuits won’t care on the assembly floor. We do plenty of 0.4 mm parts so a 0.45 isn’t anything new. The most important thing to remember is to use the right footprint. It’s easy enough to accidentally use a QFP footprint when you have a QFN (like here). I could see it being even easier to swap for the wrong footprint with this part. Doing so would be bad, most certainly. You might get one or two contacts per side on the right footprint, but that’s pretty much as good as none.

Duane Benson
It’s like Ice-9. The same, only different.

http://blog.screamingcircuits.com/

Scoopage

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I wrote recently about segmenting your solder paste stencils for the big open areas on your QFNs. The idea is that if the entire area is left open, it may end up with too much solder in the heat slug area, causing the part to lift up and not solder properly.

QFN center void CadstarGuy commented: “Also — when you have the full aperture in the stencil it can tend to drag as it is pasted leaving big gaps in the solder (and excess solder on the screen).”

That’s a very important point to remember. Ironically, leaving the area fully open can lead to either too much solder or not enough solder. Weird. Huh? The solution is the same: segment your stencil layer inside that center pad area.

Duane Benson
Anoid the void!

http://blog.screamingcircuits.com/

Funky QFN Land Patterns

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I’ve described the optimal way to create your land and solder paste layer for QFNs a couple of times before. Complex QFN land pattern But that was for a standard square QFN or rectangular DFN. What happens if you look at the bottom of your QFN and it’s all weird like this one?

Does it require a different philosophy for the big pad areas? Should it just be a solid opening because their is more than one thermal pad and they don’t cover the whole area?

Well, the image is an Intersil ISL8200 power module. It’s pretty cool and Intersil was kind enough to actually put the paste layer recommendations right in the data sheet. Unfortunately, not all chip manufacturers do that.

The bad news is that it’s a pretty complex pattern. The good news is that the data sheet gives a diagram with great detail on the required dimensions for the lands and the stencil. And, yes, you treat this just like any other QFN thermal pad. They recommend 50 – 80% paste coverage for the thermal pads just like everyone else. That means that you’ll segment the paste cut-outs in the paste layer for each of the four thermal areas just like you would for the whole pad area on a standard QFN. The data sheet for this part has the specifics.

For similar parts from other manufacturers, you should go to their datasheets and app notes first, but if you don’t find a recommendation, we would suggest doing the segmenting and shooting for somewhere between 50 and 80% coverage. Putting down too much paste is a bad idea for any QFN or DFN, but it’s probably even more critical with a part like this where the solder areas only cover half the part. If there’s too much solder on the underside, it will likely tilt and most likely not solder reliably.

Duane Benson
Don’t eat paste.

http://blog.screamingcircuits.com

10 Electronic Things to be Thankful For in 2009

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It’s that time of year when we take stock of what’s good in our little worlds. Since I’m writing this on my work blog, I’ll keep my top 10 items focused on work-related thingys.

Number 10: Allocation!? Well, maybe. Nobody likes parts shortages and allocation, but maybe, just maybe, it means that we’re seeing the light at the end of the recession tunnel.

Number 9: The mighty QFN. Yes, I know the package can be a pain to layout properly, but the size reductions we can get with it are pretty cool. It used to take something like a TO-220 or D2Pak to drive an amp of current drain, but some of these new devices can do it in a little QFN (properly laid out, of course) form-factor.

Number 8: 99.47% on-time delivery in the last year. That’s less then one job late per month – and remember, if we’re one day late, the assembly is half off and if we’re two day’s late, the assembly is free.

Number 7: The Beagleboard being open source. It’s really opened up the world of high-end non-i86 embedded processors to a very large segment of the industry that just couldn’t quite get there before. Well done Beagleboard folks!

Number 6: The Internets. Back in the olden days when I was burning my fingers soldering up discrete transistors and plain TTL and such, I had a shelf of data books. I think I may still have an old purple National Semiconductor TTL data book buried in a box somewhere. It was always cool to page through those data books, and, of course, I didn’t need to be online in order to find what I needed, but heck, I can find it all now and even more without getting up and walking across the floor to my book shelf. In fact, I pretty much don’t have to move at all anymore thanks to the Intertubes.

Number 5: Google translator. Earlier today, I got an email written in German. Before online translators, I wouldn’t have been able to do anything with it and I would have missed a very big opportunity. The email was from a barrister in the tiny country of Togo. Apparently, he’s been looking for an heir to pass an inheritance to and can’t find one. He said that he went to the American embassy and they suggested me. If not for the Google translator, I would have missed out on this wonderful opportunity to get seven million dollars transferred right into my bank account.

Number 4: Level translators. It’s still a pain to deal with interfacing signals at different voltage levels; like a 5V I2C device to a 3V I2C bus to a 1.8V GPIO, but it was way more of a pain before easy to use level translator chips became widely available. Especially the bi-directional chips. Much more convenient.

Number 3: Better static protection built into chips. Yes, we still religiously use static ground straps. We have a conductive floor and wear foot straps and anti-static jackets and have anti-static stuff all over the place, but chips are so much more robust then they used to be. I can remember the old 4000 series CMOS chips. It almost seemed like if you breathed wrong, they’d get zapped.

Number 2: The LGA form-factor package. Just kidding. LGAs are annoying. Sure, there are some redeeming qualities: low profile, a RoHS part can go both leaded and unleaded, decent heat transfer. But, they also don’t flex as well as a BGA and the pads have the disdvantages of both BGA and QFN packages. Basically, they’re just annoying.

Number 1: And the number one electronic thing that I’m thankful for are these little Flash 8-bit microcontrollers like the PICs (that I use) and Atmels (like the Arduino uses). Holy mackerel, they make life a lot easier. All that GPIO, no support chips. And, self programmable flash. Ahhhh … Anybody out there still have a UV EPROM eraser?

Duane Benson
Embedded in my head

http://blog.screamingcircuits.com/

Tented QFN/QFP Via-in-Pad

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Below is a pretty decent example of mask-tented vias in the thermal pad of a QFP. Most manufacturers recommend no more then 100 – 125 microns wider than the via to minimize voiding and thermal insulation in cases like this. This is a reasonably inexpensive way to handle vias in the thermal pad. Sometimes though, the tents will pop open, allowing solder to wick down through the via.

The mask over the center via on the right looks a little thin, so you’d want to give it an extra look over after reflow to make sure it’s okay. (We’d do that here, of course.)

We’d rather not see this technique on really small parts because it gets difficult for the fabricator to put down the mask with enough precision. With small parts, filling and plating over the vias is the preferred technique. Well, that’s always the preferred method. It’s just more important with smaller parts and BGAs. This method is acceptable for most QFPs and larger QFNs, though.

Duane Benson
All your via are belong to us

http://blog.screamingcircuits.com/