Minimizing Graping

Folks, 

This post is an excerpt on graping, from Indium Corporation’s The Printed Circuits Assemblers Guide to Solder Defects.

Introduction 

The growth of personal electronic devices continues to drive the need for ever-smaller active and passive electrical components. This miniaturization trend, together with the demands for RoHS-compliant Pb-free assembly, has created more challenges, including the graping effect.

As a solder paste deposit decreases in size, the relative surface area of exposed solder particles increases, and the amount of available flux to remove surface oxides decreases. Compounding this is the additional heat necessary to reflow most Pb-free solders, resulting in a formula conducive to producing the graping phenomenon. During the heating process, as the flux viscosity decreases and begins to spread downward and outward, the solder particles are exposed at the top of the solder paste deposit. If there is no flux in proximity, these solder particles may become oxidized when the solder paste enters the ramp or soak stage of reflow. These oxides will inhibit the full coalescence of the particles into a uniform solder joint when the solder is liquidus. The unreflowed particles often exhibit the appearance of a cluster of grapes, as can be seen in Figure 1.

Figure 1. The graping effect.

Stencil Printing

The area ratio (AR) is a critical metric in successful stencil printing. It is defined as the area of the stencil aperture opening divided by the area of the aperture sidewalls. Figure 2 shows a schematic for square/rectangular and circular apertures. A simple calculation shows that the AR is simplified to the diameter (D) of the circle divided by four times the stencil thickness (t) or AR=D/4t. Somewhat surprisingly, the result is the same for square apertures, with D now equal to the sides of the square. For the AR of a rectangular aperture, the formula is a little more complicated: ab/2(a+b)t, where a and b are the sides of the rectangle.

Figure 2. Aperture schematics for rectangular and circular apertures.

It is widely accepted in the industry that in order to get good stencil printing, the AR must be greater than 0.66. Experience has shown that if the AR <0.66, the transfer efficiency could be low and erratic, although this has gotten better with advances in solder paste technology.

Transfer Efficiency

Transfer efficiency, another important stencil printing metric, is defined as the volume of the solder paste deposit divided by the volume of the aperture. To accommodate fine-feature stencil printing, it is not uncommon to look at solder paste that incorporates finer powder in order to optimize the printing process. However, as the size of the powder particles within the solder paste decreases, the relative amount of surface area exposed increases. With this increase in surface area, an increase in total surface oxides is also introduced. This increase in surface oxides requires the flux chemicals to work even harder at removing the oxides and protecting the surfaces of the powder, component, and board metallizations during the entire reflow process.

On a 3mil-thick stencil, the AR for a 6mil square aperture is the same as the AR for a 6mil circular aperture: 0.50. However, when comparing the two, the volume of the square solder paste deposit is greater (~108 cubic mil) than the circular deposit (85 cubic mil). The additional solder paste volume provided by the square aperture may help reduce graping. Of greater importance, though, is the increased transfer efficiency provided by the square aperture. The square aperture design provides more consistent transfer efficiency, further reducing the potential for graping as inconsistent deposits could mean less volume.

SMD vs. NSMD Pads

Results from solder masking experiments have shown that the graping effect is less prevalent for the solder mask defined (SMD) pads. It is believed that the solder mask provides a barrier (dam), restricting the spread of the flux during the heating process, and increases the potential availability of the flux to remove oxides and protect from further oxidation. The solder mask can also act as a barrier to protect the solder paste powder particles in close proximity from further oxidation.

Water-Soluble vs. No-Clean

No-clean flux chemistries are generally rosin/resin-based (hereafter referred to only as resin) formulas. Because resins are not very soluble in the solvents used in water-soluble flux chemistries, they are typically replaced with large molecular compounds, such as polymers, in water-soluble fluxes. The activator(s) within the flux chemistry removes the current oxides on the joining surfaces, as well as the solder paste powder particles within the solder paste itself. Further oxidation/re-oxidation does occur during the heating stage. Whereas the resins in no-clean fluxes are excellent oxidation barriers and protect against re-oxidation, the lack of resins in water-soluble chemistries cause them to fall short in terms of providing oxidation resistance.

Hence, for the same reflow profiles—though water-soluble chemistries are generally more active—the lower oxidation resistance of water-soluble chemistries makes them more sensitive in long and/or hot profiles, increasing the potential for graping defects.

Ramp-To-Peak vs. Soak

For many years, the “soak type” reflow profile was quite prevalent. Over time, however, focus has shifted to ramp-to-peak (RTP) as the preferred reflow profile. Contributing to this shift is the higher reflow process temperatures associated with Pb-free solders, as well as the need to diminish the total heat exposure of the smaller paste deposits and temperature-sensitive components and board laminate. Another benefit of the soak profile is its utilization to reduce voiding. However, it is not as effective with Pb-free solders, due to the increased surface tension of Pb-free solders and the higher temperature used to reflow them.

To minimize graping, a reduced oven time is better, provided you use the same time-above-liquidus (TAL) and peak temperature, see Figure 3. The soak profile typically produces more graping than an RTP profile. The graping effect is exacerbated as the total time in the oven increases. Decreasing the total heat dramatically decreases the graping effect. A ramp rate (from ambient to peak) of 1°C/second is commonly recommended, which equates to approximately 3 minutes, 40 seconds to a peak temperature of 245°C.

Figure 3. Typical reflow Pb-free profiles.

Conclusions

To reduce the graping effect, it is vital to ensure an optimal printing and reflow process. Using the guidelines provided for the area ratio and good process/equipment setup will ensure good transfer efficiency. Though the area ratio for circular and square aperture designs may be equal, the potential for graping increases with circular aperture designs due to decreased paste volume and decreased transfer efficiency.

From a reflow standpoint, decreasing the total heat input will decrease the likelihood of the effect. Using an RTP-type profile with a ramp rate of ~1°C/second is suggested.

Material factors also influence the outcome. The observance of graping increases as the solder paste particle size decreases and the area of surface oxides increases. Water-soluble solder paste chemistries do not provide the oxidation barrier that resins do for no-clean chemistries and are more prone to the graping effect.

Cheers,

Dr. Ron

Optimizing Test Cost Webinar

There are many cost drivers in today’s electronics manufacturing environment. That is why it is important to eliminate unnecessary cost wherever possible.

In a new free webinar, Optimizing Test Cost, EDM’s test engineering team discusses how best to optimize inspection and test strategy. Product design considerations, automation, standardization and best mix of test technologies are discussed. Test robot options will also be demonstrated. The webinar length is 20 min with a 5-minute Q&A.

Date: Tuesday, November 2, 2022

Time: 11 am Eastern Time

To register, click here.

Grounded! What The Electronics Industry Can Learn from Airlines

Anyone who has boarded a plane in the past several months knows this all too well: the near-term future of airlines is up in the air.

From smallest to largest, all the carriers have been dramatically affected by the post-Covid rebound in passenger air travel. Delta and United Airlines each cut 30% of their respective staff in 2020.

And while many observers point to the attractive buyouts the carriers dangled before critical employees (read: pilots) as means to cut costs amid the mass groundings during the pandemic, employment has shot up over the past 18 months.

Take Delta, for instance. The second-largest airline in the world has hired 18,000 new employees since January 2021. But even with its staffing back to 95% of what it was pre-Covid, capacity reportedly is some 10 percentage points lower. Reason: it takes time to train the newbies.

“The chief issue we’re working through is not hiring but a training and experience bubble,” said Ed Bastian, CEO, Delta.

And the more complicated the job, the longer the training period. Which reveals yet another crack in the fuselage: a lack of trainers. To wit: American says its pilots are basically stuck waiting for training classes to open up, as the number of new hires far outpaces the available slots. The backlog is said to be six months or more.

The issue runs so deep, it has its own name: the Juniority problem.

United has gone on the offensive, blaming — who else? — the government. United chief operating officer Jon Roitman estimates “over 50% of our delay minutes and 75% of our cancels in the past four months were because of FAA traffic management initiatives.”

But all this comes back to the industry’s lack of foresight — or unwillingness — to continue to invest in its workers during the inevitable economic cycles.

You know where I’m going with this.

The PCB industry is historically boom/bust. We are coming off a run of very strong years, and the forecast, according to Dr. Hayao Nakahara, the preeminent researcher in the industry, continues to look bright.

But the graying of the industry is very real, and its long past time OEMs invested in recruiting and training the next generation of designers, design engineers and manufacturing engineers. (And yes, I am pointing at OEMs, since they are top the of the pyramid and ultimately their needs are the driver for the rest of the supply chain’s decision-making.

Let’s learn from the airlines, or, more precisely, their mistakes. It’s time for the push to onboard the next generation of engineers to take flight.

Conductor Sizing Software: How Much is Knowledge Worth?

My name is Mike Jouppi and I am the sole owner of a software application for sizing electrical traces in Printed Circuit Boards.  A description of the application is here.  

I would like to sell this software application and all of the material that went into creating it.  My company has developed 68 design charts.  It also has the capability to create charts for any technology and tools to import the results into the software application.

The electronics design community has started to recognize the importance of the pre-design phase of conductor sizing.  Altium has incorporated IPC-2152 for trace sizing and has training on the topic.  There are many calculators on the Web that are applying IPC-2152 design charts.

Unfortunately, very few understand the physics behind what they are employing as a tool and continue to add confusion to the electronics design community.

If you are interested in contacting me for a conversation on this topic and having a discussion about purchasing my company’s software, my email and phone number are provided below.

Mike Jouppi

Thermal Management LLC

303-359-3280

www.thermalman.com

Irene Sterian: In Memoriam

I am heartbroken to share the news that Irene Sterian passed away on May 8. Irene was director, technology and innovation development at Celestica, and before that held engineering roles at IBM.

But she is better known as the always cheerful mentor to younger engineers through SMTA, the REMAP technology accelerator she founded, and before that, NGen Canada,  Canada’s Advanced Manufacturing Supercluster.

She is survived by her husband, three children, brother and mother, not to mention legions of colleagues and friends.

For details on how to remember her, please click here.

Done Deal

The Printed Circuit Engineering Association (PCEA) today announced it has closed the acquisition of the functional assets of UP Media Group Inc., including its industry leading publications and trade shows.

The deal, which was announced during the PCB West conference and exhibition last October, includes the annual PCB West and PCB East trade shows; PRINTED CIRCUIT DESIGN & FAB (PCD&F) and CIRCUITS ASSEMBLY magazine; the PCB UPdate digital newsletter; the PCB Chat podcast series; the PCB2Day workshops and webinars; and Printed Circuit University, the dedicated online training platform.

Printed Circuit Engineering Association (PCEA) (pcea.net) is a nonprofit association that promotes printed circuit engineering as a profession and encourages, facilitates, and promotes the exchange of information and integration of new design concepts through communications, seminars, workshops, and professional certification through a network of local and regional PCEA-affiliated groups. PCEA serves the global PCB community through print, digital and online products, as well as live and virtual events. Membership is free to individuals in the electronics industry.

If You Thought Foxconn Is Just a Manufacturer …

… Think again.

Foxconn, the world’s largest EMS/ODM, with annual revenues now topping $200 billion (!), said this week it now has more than 54,000 invention patents worldwide.

Some 63% of them have been issued in the US (17,600 patents) and Japan (16,200).

Among the most common technology areas:

  • Computer accessories 17%
  • Semiconductors 14%
  • Processing and detection technologies 13%
  • Robots and optoelectronics equipment 12%
  • Display equipment 11%

If you wonder what the end-game is, think worldwide monopoly.

What’s Old is News

God love the Internet.

Nothing ever ages. Or, better said, anything can be reborn in a moment.

Take for instance, today’s report in DigiTimes.

“India officials are allegedly subsidizing US$10 billion in semiconductor manufacturing, according to Reuters citing knowledgeable sources.”

A quick review of Reuters stories over the past 90 days show no such reporting, however.

Is DigiTimes wrong?

Nope. But one must go back to Mar. 31 to find the piece: “India is offering more than $1 billion in cash to each semiconductor company that sets up manufacturing units in the country as it seeks to build on its smartphone assembly industry and strengthen its electronics supply chain, two officials said.”

This happens a lot, actually. I got a kick out of a recent recycling by multiple industry news aggregators that claimed Epec has acquired NetVia.

“Hmmm,” I thought. “That’s weird.” Because I am pretty confident that already happened.

And sure enough, that deal dates to November 2020.

What happens is that aggregators use alerts to find news, and crawlers sometimes bring old information back to the surface. Unsuspecting or inattentive editors grab the “new story” and link to it for that day’s newsletter.

And everything old is new again.

Tin Whiskers 101: Part 2: What Causes Them

Folks,

Continuing our series on tin whiskers. In the last post we discussed what they are. in this post we will discuss what causes them.

Tin whiskers are primarily caused by compressive stresses in tin. The most common cause of the stresses is copper diffusion into the tin as seen in Figure 1a. Such diffusion is common when tin is plated, melted or evaporated on copper. Copper preferentially diffuses into tin exacerbating tin whisker production.

Figure 1. Some causes of tin whiskers

 Another cause of tin whiskers can occur when the tin is plated, melted or evaporated on a material that has a lower coefficient of expansion than the tin, such as alloy 42 or ceramic. When temperature increases, the tin is constrained by the lower coefficient of expansion material. This constraint causes compressive stresses in the tin that can result in tin whiskers. See Figure 1b.

Less common causes are corrosion, as seen in Figure 1c and mechanical stresses as seen in Figure 1d.

Since copper diffusion is one of the most likely causes of tin whiskers, this mechanism deserves elaboration. The left image in Figure 2 depicts the mechanism of copper diffusion into tin. The mechanism is so strong that the diffusion of the copper often leaves voids in the copper. Such voids are called Kirkendall voids. The right image in Figure 2 is an x-ray map of copper (green) diffusing into the tin (black).

Figure 2. Copper diffusing into tin.

Clearly, one way to minimize this type of tin whisker growth is to prevent copper diffusing into tin. In a future post, we will discuss this and other tin whisker mitigation techniques. 

Cheers,

Dr. Ron

Best Wishes,

Gray Mattered

I am sad to report the passing of Foster Gray, the brilliant Texas Instruments engineer who over his 41 years earned eight patents, 27 technical publications, and four published papers.

I worked with him at IPC, where he participated or led dozens of standards and round robin studies, and he was always prepared and always a gentleman.

His obituary can be seen here.