The other day, I wrote about vias near pads. The post got a couple of interesting comments.
In one of the comments, Mitch said, “When I was learning PCB design in the 1980s, I was taught by a mentor that understood assembly very well.” I think that highlights a big component of the problem. I suspect that a lot of folks doing layout today were not taught by anyone but themselves.
CAD packages may have instruction manuals and tutorials, but learning how to use a software package is a lot different than learning how to do the actual process well. It’s possible to be very proficient at using a word processor, but still not know how to write well.
It’s not an uncommon scenario these days, especially after the economic suckiness of last year, to come in to work expecting to hand off a schematic to the layout engineer only to find that “tag you’re it.”
Howard, in another comment, suggested that in his experience, filling and plating over vias in pads typically only adds about 8% to the PCB cost. In smaller prototype quantities, it may be a little more then that, but what’s the cost of a failed assembly? If you have the room to move the vias off the pads, the only cost may be in layout time. If space is critical or if there are signal/noise/thermal issues that force the vias to be in the pads, then you’ll just have to spend the extra to fill and plate.
If you do find yourself suddenly tasked with layout and you’ve never done one before, find a mentor (or maybe a Minotaur), read up online, call up a manufacturing person, study the Screaming Circuits blog. What ever you do, figure out all these little traps like vias in pad, components library foot print issues, spacing issues, thermal issues, etc. Then dive into the layout and learn from each one. Drink some tea too. It can relax you. Just try to stay away from Oreos and ice cream late at night.
What’s the deal with 1729?