Vias don’t go well in pads, of course. In fact, I think it’s fair to say that vias go as well in pads as large igneous rocks go in peanut butter and jelly sandwiches.
But it’s not just vias in pads that annoy people. Vias near pads can be pretty much a nuisance too. In the SOIC pictured below, the pin 1 lead is at risk of having the solder wicked off the pad and down into the via.
If you’ve got to have a via right near a pad like that, always make sure there is something between the pad and the via that will keep the solder away. A thin line of solder mask, or even silk screen, like with the pads and vias on pins 12 and 14, will do. Anything to stop the solder from going where you don’t want it to go.
Obviously these designs were done by someone that has no knowledge of the assembly processes.
When I was learning PCB design in the 1980s I was taught by a mentor that understood assembly very well. That was long before I saw anything from IPC. He made me very aware of DFM and DFA issues. I would suggest ANYONE learning PCB design today – find an assembly house and visit their lines, or find an ‘old timer’ like myself to learn from.
BTW, I’ve seen worse things lately that CAN’T be worked around in assembly.
the pictures for your examples are HUGE and would definately wick the solder away from the pads.
if via in pads are required for space considerations then the appropriate size vias need to be used and the vias need to be plugged or filled.
one of the assembly vendors has the following in their spec: Vias are filled with a non conductive, plugging paste that is then plated with copper. This enables significant density increase without implementing micro vias, but may also be used as a buried via used in conjunction with a stacked micro vias.
Sizes: The typical Drilled Hole Size is 10 to 30 mils. The Finished Hole Size (FHS) range is 8 to 26 mils. The aspect ratio of 10:1 should not be exceeded for PCB thickness to FHS. If multiple hole-sizes are to be filled each application may span a range of 5 mils. Example: One application could fill FHS with 8, 10 and 12 mils.
Uses: The pads are suitable for via in SMT pads. BGA balls and other components may be directly mounted to the via pads, so long as the pad shape is effectively controlled. 0402 chips mounted opposite of a 1mm pitch BGA is a common application.
Cost: Typical 8% increase.
Cost difference between one plug and 5000 plugs is nominal.
Not all board houses provide this service.
Board Finishes: All
Process: Copper plating, non- conductive fill of vias, planarize outer layers of PCB (remove residue), plate copper over the top of vias, 2nd planarize, apply solder mask, apply board finish
Performance: 100% of targeted vias are plugged shut. The maximum dimple depth in the copper shall be 1 mil. The outer layer copper is planarized down to final thickness, so outer layer minimum space and trace limited by 1 mil over standard processing. Example: If the fabrication house can normally perform 3 mil space / 3 mil trace on outer layers, they may be limited to 4 mil space / 4 mil trace using this process.
Typical Materials: LPI Solder mask, Peter’s Plugging Paste or equivalent.
We have had success with letting the soldermask “encroach” the via pads (leaving the hole exposed) which allows vias to be placed much closer to pads and still have a mask dam between them.