I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?
That’s a good question. I’ve heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.
Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?
Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?
If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You’ll have to make sure that your board fab house can give you an accurate thickness of the via wall.
If you know the via current capacity, can you calculate the past and future capacity?