The race for the smallest part is still going strong. That and the fact that basic logic gates are still with us is affirmed quite well with a new set of chips from NXP. The 74AUP2G00 is a dual two-input NAND gate in a no lead XSON8 package at just 1 x 1.35mm. That’s not the scary part. The scary part is the lead pads under the part are 0.15mm wide and just 0.35mm pitch center to center. That’s 0.0059″ and 0.0138″ respectively. The gap between the pads is 0.2mm (0.0078″).
To put that in a little bit of perspective, an 0201 passive component is 0.024″ x 0.012″. An 01005 is 0.016″ x 0.008″.
Above is a land pattern for the part with an 0201 bypass cap next to it. The trace going from the pin to ground (Pin 4) is an 0.008″ trace. The trace going to VCC (pin 8) is 0.006″. The via is a pretty standard 0.024″via. As you can see, an 0.008″ trace and space isn’t going to do for a board with this size of part on it. Even 0.006″ is really a bit too big.
La de da de de, la de da de da
Below is a pretty decent example of mask-tented vias in the thermal pad of a QFP. Most manufacturers recommend no more then 100 – 125 microns wider than the via to minimize voiding and thermal insulation in cases like this. This is a reasonably inexpensive way to handle vias in the thermal pad. Sometimes though, the tents will pop open, allowing solder to wick down through the via.
The mask over the center via on the right looks a little thin, so you’d want to give it an extra look over after reflow to make sure it’s okay. (We’d do that here, of course.)
We’d rather not see this technique on really small parts because it gets difficult for the fabricator to put down the mask with enough precision. With small parts, filling and plating over the vias is the preferred technique. Well, that’s always the preferred method. It’s just more important with smaller parts and BGAs. This method is acceptable for most QFPs and larger QFNs, though.
All your via are belong to us