I recently posted that circular apertures deliver much less solder paste than square apertures. One of the obvious reasons is that a circle of diameter D has only 78.5% of the area of a square of side D. However, in addition, the circular aperture has poorer release than a square aperture. In the aforementioned post, I theorized that the reason for the poorer release is that the curved surface of the circular aperture adheres to the solder paste solder balls more effectively.
I recently thought of the above situation in light of the “Five Ball Rule.” This rule states that the solder paste’s largest solder particle diameter should be such that at least five of these particle diameters would span the width of a rectangular stencil aperture.
See Figure 1 for the Five Ball Rule applied to circular and square apertures. Note that the ratio of solder balls is 19/25 = 76%, almost the theoretical maximum ratio. However, for square and circular apertures, the ‘Eight Ball Rule” is suggested. But, in some configurations the Eight Ball Rule may result in less solder paste — 40/60 = 62.5% (Figure 2). It should be remembered that this is just a surface area argument, not a volume argument. Solder paste is printed in volume and in this discussion we are just looking at one layer of paste.
However, the bottom line is that square apertures should be preferred over circular apertures.
In my lastpost, I shared about an Excel–based software tool called Line Balancer to help candidates for SMTA Certification prepare for the line balancing part of the program. They can use Line Balancer to check the correctness of practice line balancing problems. This post will discuss another Excel-based software tool, Reflow Profiler, to help candidates prep for the reflow profiling part of the certification.
Typically, the reflow profiling goal is to determine if the reflow profile matches the requirements of the solder paste specification.
As an example, let’s consider a reflow profile as shown in Figure 1. The solder paste specification is shown in Figure 2. We will first solve the problem by hand and then use the software.
The first task is to determine if the ramp-to-peak rate matches the solder paste specification outlined in red in the specification shown in Figure 3. By measuring the change in temperature in Figure 4 from point A to B and dividing it by the change in time from those points, we see in Figure 4 that the ramp-to peak-rate is 0.857°C/sec., and is within the recommended specifications 0.5 to 1.0°C/sec.
Figure 5 shows the solder paste specification with the time above liquidus (TAL) with the peak temperature highlighted. While Figure 6 shows the reflow profile, where the TAL is measured as 60 seconds and the peak temperature at 240°C, both are consistent with the recommended values.
Lastly, Figure 7 shows the solder paste specification with the cooling ramp rate highlighted and Figure 8 shows the reflow profile with the cooling rate calculated as -2.8°C/s, again within the specification.
If you are interested in a copy of Reflow Profiler send me an email at [email protected].
I recently developed some Excel-based software to help those who are planning to take the SMTA certification exam to practice.
In this post, I will discuss the tool that performs line balancing. In a typical SMT assembly line, the placement machines are the “gate” in the cycle time of the line. To assure that their cycle time is the lowest, the placement machines must be time balanced. For example, suppose a simple SMT assembly line has one chip shooter and one flexible placer. Let’s say that the chip shooter takes longer to place all of the chips than the flexible placer takes to assemble the simple and complex integrated circuits. So, in this case, chips should be removed from the chip shooter and be placed on the flexible placer. But how many should be moved to the flexible placer? Determining the number requires algebra, and to understand how to do it, we need a numeric example.
Let’s do an example. In an assembly line, the “gate” in the cycle time is component placement.
The chipshooter (CS) places passives at 60,000/hr and Simple ICs (SICs) at 4,000/hr
The flexible placer (FP) places complex ICs (CICs) at 3,000/hr and SICs and passives at 8,000/hr
The bill of material (BOM) is 354 passives, 12 SICs, and 4 CICs
If the FP takes less time to place the CICs and SICs than the CS takes to place all of the passives, then move some of the passives to the FP to time balance the line
Let’s check the situation that the FP takes: (4 CICs / 3,000/hr) + (12 SICs / 8,000/hr) = 0.001333 + 0.0015 = 0.002833hrs
The CS takes: 354/60,000/hr = 0.0059hrs
So, move chips to the FP—but how many? Let’s call the number x. The times should be equal, so:
0.002833+x/8000 = (354-x)/60,000. Solve for x to time balance the line.
0.002833+x/8000 = (354-x)/60,000, multiply each side by 60,000
(60,000*0.002833) + (60,000x/8000) = 354 – x
170 + (60/8)x = 354 – x, gather x terms
170 + ((60/8) +1)x = 354, gather numbers
(68/8)x = 354-170 = 184, solve for x
x = (8/68)*184 = 21.65 or 22 passive moved to FP
Let’s see if the times on each machine are the same.
CTCS= 332 passives/60,000 passives/hr =0.005533 hrs or 19.92 secs
In our last post, we discussed techniques to mitigate tin whiskers (TW). To help determine what your tin whisker mitigation strategy should be, consider using failure modes and effects analysis (FMEA). The central metric of FMEA is the risk priority number (RPN). For tin whiskers, the RPN is equal to the product of: (1) the probability of tin whiskers (P); (2) the severity, if a tin whisker exists (S); and (3) how hard it is to detect a tin whisker (D). In equation form:
RPN = P*S*D
As a first example, consider a consumer product, like a mobile phone with a life of 5 years. With mitigation, on a scale of 1 to 10, P might be 2. For S, we might rate it at a 3, as a failure in the device is unlikely to cause severe harm to anyone. Detection (D) is a problem because the tin whiskers that form later cannot be detected during manufacturing; hence, we would have to rate D as a 10. So, the RPN is: 2*3*10 = 60, which is not too high. Therefore, with P and S at relatively low values, a tin whisker mitigation strategy would likely be successful for any consumer product. It should be pointed out that determining the RPN numbers would almost certainly require supporting data, brainstorming sessions, and a buy-in from the entire product team. The team would also have to determine any appropriate mitigation strategy such as avoiding bright tin coatings on component leads and perhaps using a flash of nickel between the copper and the tin (Figure 1).
Figure 1. In mission-critical products, coatings may be required. It is almost impossible for a TW to penetrate both layers of coating as shown above.
Now consider a mission-critical product, such as certain types of military equipment. If we assume that the electronics have a service life of 40 years and that a failure could cause bodily harm or death, we could likely end up with a consensus that RPN = 10*10*10 =1000, the highest RPN possible. This situation would demand that special tactics be used to address the tin whisker risk. These tactics were discussed in my paper and presentation given at SMTA Pan Pacific 2019.
In the last post on tin whiskers, we discussed detection. In this post, we will cover mitigation. Since compressive stresses are a primary cause of tin whiskers, minimizing these stresses will help to mitigate tin whisker formation. There are several approaches to accomplish this compressive stress reduction. The first is to establish a process that produces a matte finish as opposed to a bright tin finish. Experience has shown that a satin or matte tin finish, which has larger grain sizes, has lower internal compressive stresses than a bright tin finish. Studies have shown that avoiding a bright tin finish alone can reduce tin whisker formation by more than a factor of ten. Thicker tin layers will often reduce compressive stresses.
Since a major source of the compressive stresses in tin is due to copper diffusion into the tin, minimizing this diffusion will significantly reduce tin whisker formation. One proven approach to minimizing copper diffusion is to have a flash of nickel between the copper and the tin. Since nickel does not readily diffuse into the tin after initial intermetallic formation, tin whisker formation can be all but eliminated in many cases.
Adding bismuth to the tin, in small amounts, can also reduce tin whisker formation. The bismuth solid solution strengthens the tin. This strengthening will often reduce tin whisker formation.
Another mitigation approach is the use of coatings. Acrylics, epoxies, urethanes, alkali silicate glasses and parylene C have been used. Parylene C appears to be the most promising.
Often a tin whisker will penetrate the coating as seen in Figure 1. However, to be a reliability risk, it must penetrate a second coating.
Figure 1. A tin whisker about to penetrate a polymer coating. Source: Dr. Chris Hunt, NPL.
This situation is almost impossible as the tin whisker is fragile and will bend as it tries to penetrate the second layer of coating. See Figure 2. So, coatings can be a very effective tin whisker mitigation approach.
Figure 2. To be a reliability concern, a tin whisker must penetrate two protective coatings.
The next and last tin whisker post will be on using FMEA (failure modes and effects analysis) to develop a tin whisker reduction strategy.
One of the great challenges of tin whiskers is detecting them. When one considers that their median thickness is in the 3 to 5 micron range (a human hair is about 75 microns,) they can be hard to see with direct lighting. Right angle lighting facilitates visual detection. See Figure 1. In this figure, Panashchenko shows that with direct light (left image), it is impossible to see the tin whisker, however with right angle light the tin whisker jumps out.
Figure 1.* It is not possible to see the tin whisker with direct lighting as in the left image. However, in the right image, right angle lighting makes it easy to see the tin whisker.
Start with low magnification and work up to high magnification
Have the ability to tilt the sample in 3 axes
Use a flexible lamp that allows multiple angles of illumination, do not use a ring light
Use a LED or fiber optic lighting, not incandescent lights which can cause shadowing
Vary the brightness of the light source
The most important tip is to vary the angle of lighting while varying the magnification. Thus, analyzing a sample should take several minutes, at least. However, even the most thorough inspection may miss some tin whiskers.
In the next post, I will discuss mitigation techniques.
*The image is from Lyudmila Panashchenko, “The Art of Metal Whisker Detection: A Practical Guide for Electronics Professionals,” IPC Tin Whisker Conference, April 2012.
Continuing our series on tin whiskers. In thelast post we discussed what they are. in this post we will discuss what causes them.
Tin whiskers are primarily caused by compressive stresses in tin. The most common cause of the stresses is copper diffusion into the tin as seen in Figure 1a. Such diffusion is common when tin is plated, melted or evaporated on copper. Copper preferentially diffuses into tin exacerbating tin whisker production.
Figure 1. Some causes of tin whiskers
Another cause of tin whiskers can occur when the tin is plated, melted or evaporated on a material that has a lower coefficient of expansion than the tin, such as alloy 42 or ceramic. When temperature increases, the tin is constrained by the lower coefficient of expansion material. This constraint causes compressive stresses in the tin that can result in tin whiskers. See Figure 1b.
Less common causes are corrosion, as seen in Figure 1c and mechanical stresses as seen in Figure 1d.
Since copper diffusion is one of the most likely causes of tin whiskers, this mechanism deserves elaboration. The left image in Figure 2 depicts the mechanism of copper diffusion into tin. The mechanism is so strong that the diffusion of the copper often leaves voids in the copper. Such voids are called Kirkendall voids. The right image in Figure 2 is an x-ray map of copper (green) diffusing into the tin (black).
Figure 2. Copper diffusing into tin.
Clearly, one way to minimize this type of tin whisker growth is to prevent copper diffusing into tin. In a future post, we will discuss this and other tin whisker mitigation techniques.
Tin whiskers are very fine filaments or whiskers of tin that form out of the surface of the tin. See Figure 1. They are the result of stress release in the tin. Tin whiskers are a phenomenon that is surprising when first encountered, as their formation just doesn’t seem intuitive.
They are a concern, as they can cause electrical short circuits or intermittent short circuits as a fusible link. Lead in tin-lead solder greatly suppresses tin whisker growth. Therefore, with the advent of lead-free solders there is a justifiable concern for decreasing reliability due to tin whisker growth in electronics.
Tin whiskers can vary in length and width, as is seen in Figure 2. Note that although only about 10% are as long a 1000 microns (1mm). That length and occurrence rate is such as to cause many reliability concerns.
Figure 2. The length and width of some tin whiskers. The source is also the NASA Tin Whisker Website.
Over the following weeks I plan to post how tin whiskers form and strategies to alleviate them. Most of the information I will post comes from a paper I presented with Annaka Balch at the SMTA PanPac 2019.
NASA has an excellent website that provides much information about tin whiskers and is a source for historic critical failures caused by tin whiskers.
In a recentpost, I discussed Moore’s Law. I challenged readers to solve for “a” and “b” from the equation a*2^(b*(year-1970)) from the graph in Figure 1.
Moore’s Law posits that the number of transistors doubles every two years. If so, “b” should be 0.5. It ends up that “b”, from the solution in Figure 2, is 0.4885, so a double occurs about 1/0.4885 =2.047 years, but this number is really close to two years. The solution follows:
BTW, congrats to Indium Corporation’s Dr. Huaguang Wang as he got a close solution.
Moore’s Law was developed by Gordon Moore in 1965. It predicted that the number of transistors in integrate circuits would double approximately every two years. Surprisingly, it has held true up to today. Figure 1 shows some of the integrated circuit transistor counts as a function of time. The red line is a good fit.
Figure 1. A plot of transistor count in selected ICs as a function of the year.
A reasonable equation for the red line is Transistor Count = a*2^(b*(year-1970)). What should “b” be if the count doubles every two years? To the first person that can solve for “a” and “b” using the red line and the equation above, we will send a Dartmouth sweatshirt.